International Journal of Reconfigurable Computing

Aims & Scope

The aim of the International Journal of Reconfigurable Computing is to serve the large community of researchers and professional engineers working on theoretical and practical aspects of reconfigurable computing.

The journal seeks to promote the use of reconfigurable computing for research, education, and applications.

Original full and short papers on all aspects of reconfigurable computing, from hardware architectures and devices to custom computers and high performance systems, are encouraged for submission.

All aspects of reconfigurable computing are considered.

Since the entire field is very dynamic, areas of the interest include but are not limited to: Models, methods, tools, and architectures for reconfigurable computing Compilation, simulation, debugging, synthesis, verification, and test of reconfigurable systems Field programmable gate arrays and other reconfigurable technologies Self adaptation and dynamic reconfiguration Evolvable hardware and adaptive computing Algorithms implemented on reconfigurable hardware Hardware/software codesign and cosimulation with reconfigurable hardware High performance reconfigurable computing Reconfigurable computing education Application areas of reconfigurable computing include (but are not limited to): signal and image processing, communications, biomedical applications, consumer electronics, embedded systems, automation, intelligent systems, scientific computing, infotainment and multimedia, industrial applications, data compression, cryptography, robotics, and automotive.

Metrics & Ranking

Abstracting & Indexing

Journal is indexed in leading academic databases, ensuring global visibility and accessibility of our peer-reviewed research.

• Scopus
• Google Scholar
• Directory of Open Access Journals (DOAJ)
• Web of Science

Subjects & Keywords

Journal’s research areas, covering key disciplines and specialized sub-topics in Computer Science, designed to support cutting-edge academic discovery.

Licensing & Copyright

This journal operates under an Open Access model. Articles are freely accessible to the public immediately upon publication. The content is licensed under a Creative Commons Attribution 4.0 International License (CC BY 4.0), allowing users to share and adapt the work with proper attribution.

Copyright remains with the author(s), and no permission is required for non-commercial use, provided the original source is cited.

Policy Links

This section provides access to essential policy documents, guidelines, and resources related to the journal’s publication and submission processes.

• Aims scope
• Homepage
• Oa statement
• Author instructions
• License terms
• Review url
• Board url
• Copyright url
• Plagiarism url
• Preservation url
• Apc url
• License

Plagiarism Policy

This journal follows a plagiarism policy. All submitted manuscripts are screened using reliable plagiarism detection software to ensure originality and academic integrity. Authors are responsible for proper citation and acknowledgment of all sources, and any form of plagiarism, including self-plagiarism, will not be tolerated.

For more details, please refer to our official: Plagiarism Policy.

APC Details

The journal’s Article Processing Charge (APC) policies support open access publishing in Computer Science, ensuring accessibility and quality in research dissemination.

This journal requires an Article Processing Charge (APC) to support open access publishing, covering peer review, editing, and distribution. The current APC is 950.00 USD. Learn more.

Explore journals without APCs for alternative publishing options.

Most Cited Articles

The Most Cited Articles section features the journal's most impactful research, based on citation counts. These articles have been referenced frequently by other researchers, indicating their significant contribution to their respective fields.

• Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings

  Citation: 99

  Authors: Knut, Chik How

• FPGA Interconnect Topologies Exploration

  Citation: 47

  Authors: Zied, Hayder, Umer, Habib

• Pipeline FFT Architectures Optimized for FPGAs

  Citation: 44

  Authors: Bin, Yingning, David

• Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools

  Citation: 44

  Authors: Bruno, An, Erik H., Abdellah

• True-Randomness and Pseudo-Randomness in Ring Oscillator-Based True Random Number Generators

  Citation: 44

  Authors: Nathalie, Florent, Viktor, Boyan

• An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick

  Citation: 42

  Authors: Gianmarco, Gabriele, Emilio, Gionata, Luca

• A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network‐On‐Chip and Spiking Neural Networks

  Citation: 42

  Authors: Jim, Fearghal, Liam, Steve, Brian, Seamus

• An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

  Citation: 32

  Authors: Y. H., M., M. N.

• High Performance Biological Pairwise Sequence Alignment: FPGA versus GPU versus Cell BE versus GPP

  Citation: 32

  Authors: Khaled, Ali, Cheng, Yang, Ying, Xiang

• The “Chimera”: An Off-The-Shelf CPU/GPGPU/FPGA Hybrid Computing Platform

  Citation: 30

  Authors: Ra, David J., Susan M.