IEEE Computer Architecture Letters

Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing.

Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.

View Aims & Scope

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Metrics & Ranking

Impact Factor

Year	Value
2025	1.4

SJR (SCImago Journal Rank)

Year	Value
2024	0.496

Quartile

Year	Value
2024	Q2

h-index

Year	Value
2024	42

Journal Rank

Year	Value
2024	11671

Journal Citation Indicator

Year	Value
2024	236

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Abstracting & Indexing

Journal is indexed in leading academic databases, ensuring global visibility and accessibility of our peer-reviewed research.

• Scopus
• Google Scholar
• Web of Science

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Subjects & Keywords

Journal’s research areas, covering key disciplines and specialized sub-topics in Computer Science, designed to support cutting-edge academic discovery.

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Most Cited Articles

The Most Cited Articles section features the journal's most impactful research, based on citation counts. These articles have been referenced frequently by other researchers, indicating their significant contribution to their respective fields.

• DRAMSim2: A Cycle Accurate Memory System Simulator

  Citation: 707

  Authors: P, E, B

• Ramulator: A Fast and Extensible DRAM Simulator

  Citation: 495

  Authors: Yoongu, Weikun, Onur

• MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research

  Citation: 227

  Authors: A.J., D.J.

• DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator

  Citation: 219

  Authors: Shang, Zhiyuan, Dhiraj, Ankur, Bruce

• NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

  Citation: 195

  Authors: Matthew, Tao, Yuan

• gem5-gpu: A Heterogeneous CPU-GPU Simulator

  Citation: 163

  Authors: Jason, Joel, Marc S., Mark D., David A.

• Fast Bulk Bitwise AND and OR in DRAM

  Citation: 148

  Authors: Vivek, Kevin, Amirali, Donghyuk, Michael A., Onur, Phillip B., Todd C.

• Subtleties of transactional memory atomicity semantics

  Citation: 140

  Authors: C., E.C., M.M.K.

• Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

  Citation: 121

  Authors: Justin, Jichuan, HanBin, Onur, Parthasarathy

• Power Management of Datacenter Workloads Using Per-Core Power Gating

  Citation: 102

  Authors: Jacob, Matteo, Vanish, Parthasarathy, Christos

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