IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities.

Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.

View Aims & Scope

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Metrics & Ranking

Impact Factor

Year	Value
2025	2.9

SJR (SCImago Journal Rank)

Year	Value
2024	0.725

Quartile

Year	Value
2024	Q1

h-index

Year	Value
2024	136

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Abstracting & Indexing

Journal is indexed in leading academic databases, ensuring global visibility and accessibility of our peer-reviewed research.

• Scopus
• Google Scholar
• Web of Science

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Subjects & Keywords

Journal’s research areas, covering key disciplines and specialized sub-topics in Computer Science and Engineering, designed to support cutting-edge academic discovery.

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Most Cited Articles

The Most Cited Articles section features the journal's most impactful research, based on citation counts. These articles have been referenced frequently by other researchers, indicating their significant contribution to their respective fields.

• Asymptotic waveform evaluation for timing analysis

  Citation: 1374

  Authors: L.T., R.A.

• TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

  Citation: 1283

  Authors: Filipp, Jun, Andrew, Rodrigo, John, Paul, Nabil, Yutaka, Pallab, Gi-Joon, Brian, Michael, Bernard, Jente B., Rajit, William P., Bryan, Dharmendra S.

• PRIMA: passive reduced-order interconnect macromodeling algorithm

  Citation: 1024

  Authors: A., M., L.T.

• Efficient linear circuit analysis by Pade approximation via the Lanczos process

  Citation: 970

  Authors: P., R.W.

• New spectral methods for ratio cut partitioning and clustering

  Citation: 828

  Authors: L., A.B.

• NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

  Citation: 812

  Authors: N. P.

• MIS: A Multiple-Level Logic Optimization System

  Citation: 809

  Authors: R.K., R., A., A.R.

• Force-directed scheduling for the behavioral synthesis of ASICs

  Citation: 768

  Authors: P.G., J.P.

• Measuring the Gap Between FPGAs and ASICs

  Citation: 711

  Authors: Ian, Jonathan

• FastCap: a multipole accelerated 3-D capacitance extraction program

  Citation: 688

  Authors: K., J.

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